The demand for increased mobility in consumer electronics is pressuring manufacturers to scale electronic technologies (e.g., semiconductor devices) to ever smaller dimensions. At the same time, the demand for increased functionality, speed, noise elimination, etc., is forcing manufactures to increase the number of passive components (e.g., capacitors and resistors) used by consumer electronic devices. Passive component integration has traditionally been accomplished by mounting them onto package and/or printed circuit board (PCB) substrate surfaces. Restricting the location of the passive components to the substrate's surface however can limit the passive components' operational capabilities (due to their inherent distance from the semiconductor device) and the substrate's scalability.
One way manufacturers are attempting to address this is by embedding the passive components in the substrate, a technique referred to as embedded passive technology. This frees up surface real estate and facilitates substrate miniaturization. Speed and signal integrity also improves because embedded components provide a more direct path through which the IC signals propagate.
One particular area of interest with respect to embedded passive technology has been the incorporation of thin film capacitors (TFCs) into organic packaging (e.g., bismaleimide triazine resin, etc.) substrates. Among the various materials being considered for use as capacitor dielectrics are high-k ceramic materials. However, high-k ceramic materials can require processing at high temperatures (e.g., furnace annealing at 600-800 degrees Celsius) in order to achieve their high dielectric constant properties. At these temperatures, organic packaging substrates can melt.
One technique for addressing this involves mounting a pre-fabricated TFC laminate that has already been annealed onto the organic substrate. Shown in FIG. 1 is an example illustration of such a TFC laminate 2, which includes a high-k ceramic material 8, superimposed between conductive films 6 and 4. In FIG. 2, the conductive film 6 portion of the TFC laminate 2 has been patterned to define lower electrode structures 10. In FIG. 3 the partially patterned TFC 2 is then mounted to a substrate 18 that includes polymer build-up layers 11, 14 and copper build-up layer 12. The copper build-up layer 12 connects with underlying conductive structures (not shown) by way of via portions 13. Next, as shown in FIG. 4, the conductive film 4 is thinned and patterned to form upper electrode portions 21 (as shown in FIG. 5). Then, as shown in FIG. 5, via openings 22 are formed thru the high-k ceramic material, the polymer build-up layer 11, and in some cases, portions of the lower electrode structures 10, to expose underlying portions of copper build-up layer 12. As further seen in FIG. 5, a conductive material is deposited in the via openings and over the surface of the TFC where it is then thinned and patterned to form upper electrodes 26, biasing interconnects 28 for the lower electrodes, I/O interconnects, build-up interconnect structures, and/or the like.
The use of this integration scheme however is not without its problems. More specifically, any one of the processes used to pattern the lower electrodes 10, the upper electrode portions 21, and/or the via openings 22 can damage the hi-k ceramic dielectric 8 and thereby impact the functionality of the TFC.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.